The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2017
Filed:
Feb. 03, 2016
Phase locked loop (pll) timing device evaluation system and method for evaluating pll timing devices
Integrated Device Technology, Inc., San Jose, CA (US);
Leon Goldin, Otttawa, CA;
Silvana Rodrigues, Ottawa, CA;
INTEGRATED DEVICE TECHNOLOGY, INC, San Jose, CA (US);
Abstract
An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system.