Bit remapping mechanism to enhance lossy compression in floating-point applications

Abstract

Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (LSB) positions of identified floating point (FP) numbers to a uniform binary value string, mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions to recover the original floating point numbers.