The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2017
Filed:
Feb. 22, 2016
Applicant:
Marvell International Ltd., Hamilton, BM;
Inventors:
Roger Longstreet, Cheyenne, WY (US);
Vivek Raghunath Khanzode, Sunnyvale, CA (US);
Hongying Sheng, San Jose, CA (US);
Assignee:
Marvell International Ltd., Hamilton, BM;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/12 (2006.01); G01R 31/3177 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01); H03M 9/00 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G06F 13/4282 (2013.01); G06F 13/1684 (2013.01); G06F 13/385 (2013.01); H03M 9/00 (2013.01);
Abstract
A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.