The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Apr. 27, 2016
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Ean Lee, Busan-si, KR;

Jee-Soo Mok, Yongin-si, KR;

Young-Gwan Ko, Seoul, KR;

Soon-Oh Jung, Yongin-si, KR;

Kyung-Hwan Ko, Gimhae, KR;

Yong-Ho Baek, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 3/06 (2006.01); H05K 3/18 (2006.01); H05K 3/40 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H05K 1/111 (2013.01); H05K 1/183 (2013.01); H05K 3/06 (2013.01); H05K 3/061 (2013.01); H05K 3/188 (2013.01); H05K 3/40 (2013.01); H05K 3/4644 (2013.01); H05K 2201/09036 (2013.01);
Abstract

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.


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