The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Jun. 30, 2009
Applicants:

Pradeep Sindhu, Los Altos Hills, CA (US);

Gunes Aybay, Los Altos, CA (US);

Jean-marc Frailong, Los Altos, CA (US);

Anjan Venkatramani, Los Altos, CA (US);

Quaizar Vohra, Santa Clara, CA (US);

Inventors:

Pradeep Sindhu, Los Altos Hills, CA (US);

Gunes Aybay, Los Altos, CA (US);

Jean-Marc Frailong, Los Altos, CA (US);

Anjan Venkatramani, Los Altos, CA (US);

Quaizar Vohra, Santa Clara, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/931 (2013.01); H04L 12/933 (2013.01); H04L 12/947 (2013.01);
U.S. Cl.
CPC ...
H04L 49/35 (2013.01); H04L 49/00 (2013.01); H04L 49/1515 (2013.01); H04L 49/251 (2013.01); H04L 49/356 (2013.01); H04L 49/70 (2013.01);
Abstract

In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.


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