The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Mar. 13, 2014
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, Tokyo, JP;

Inventor:

Takayuki Nakai, Tokyo, JP;

Assignee:

MITSUBISHI ELECTRIC CORPORATION, Chiyoda-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/183 (2006.01); H03K 23/58 (2006.01); H03L 7/095 (2006.01); H03L 7/10 (2006.01); H03L 7/107 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
H03L 7/183 (2013.01); H03K 23/58 (2013.01); H03L 7/0891 (2013.01); H03L 7/095 (2013.01); H03L 7/10 (2013.01); H03L 7/1075 (2013.01);
Abstract

In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.


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