The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

May. 13, 2016
Applicant:

Silergy Semiconductor Technology (Hangzhou) Ltd, Hangzhou, ZheJiang Province, CN;

Inventors:

Yunlong Han, ZheJiang Province, CN;

Huiqiang Chen, ZheJiang Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 5/00 (2006.01); H02M 1/42 (2007.01); H02M 7/04 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/4216 (2013.01); H02M 1/4208 (2013.01); H02M 7/04 (2013.01); H02M 2001/0025 (2013.01); Y02B 70/126 (2013.01); Y02P 80/112 (2015.11);
Abstract

In one embodiment, a power factor correction (PFC) circuit can include: (i) a rectifier bridge and a PFC converter coupled to an input capacitor; (ii) a harmonic wave compensation circuit configured to shift a phase of a DC input voltage provided from the rectifier bridge, where the harmonic wave compensation circuit comprises a phase of about −45° when a corner frequency is about 50 Hz; and (iii) a PFC control circuit configured to control the PFC converter, where the PFC control circuit comprises a first sampling voltage, and the harmonic wave compensation circuit is configured to control a phase of the first sampling voltage to lag a phase of the DC input voltage by about 45°.


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