The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Mar. 15, 2013
Applicant:
Peter Oaklander, Saratoga, CA (US);
Inventor:
Peter Oaklander, Saratoga, CA (US);
Assignee:
Other;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); H02M 1/14 (2006.01); H02M 1/08 (2006.01); H02M 3/157 (2006.01); H02M 3/158 (2006.01); H02M 7/537 (2006.01); H03K 17/06 (2006.01); H02M 1/44 (2007.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/14 (2013.01); H02M 1/08 (2013.01); H02M 3/156 (2013.01); H02M 3/157 (2013.01); H02M 3/158 (2013.01); H02M 7/537 (2013.01); H03K 17/063 (2013.01); H02M 1/44 (2013.01); H02M 3/1584 (2013.01); H02M 2001/0009 (2013.01);
Abstract
A disclosed apparatus includes a converter for receiving a supply and regulating a load. The converter uses a gate driver that is controlled by a controller via a control loop. The control loop controls the converter in response to a feedback signal. The controller is located on a first integrated circuit and the gate driver is located on as second integrated circuit. A process geometry of the first integrated circuit is finer than a process geometry of the second integrated circuit.