The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Mar. 20, 2017
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Augustin Monroy Aguirre, St. Martin d'heres, FR;

Guillaume Bertrand, Saint Martin d'heres, FR;

Philippe Cathelin, Laval, FR;

Raphael Paulin, Le Versoud, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 23/528 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1079 (2013.01); H01L 29/1095 (2013.01); H01L 29/456 (2013.01);
Abstract

An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.


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