The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Dec. 20, 2016
Peregrine Semiconductor Corporation, San Diego, CA (US);
Buddhika Abesingha, Escondidto, CA (US);
Simon Edward Willard, Irvine, CA (US);
Alain Duvallet, San Diego, CA (US);
Merlin Green, San Diego, CA (US);
Sivakumar Kumarasamy, San Diego, CA (US);
Peregrine Semiconductor Corporation, San Diego, CA (US);
Abstract
Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.