The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Aug. 24, 2016
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Geert Hellings, Halle, BE;

Geert Van der Plas, Leuven, BE;

Mirko Scholz, Leuven, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/266 (2006.01); H01L 27/06 (2006.01); H01L 21/033 (2006.01); H01L 29/808 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/761 (2006.01); H01L 29/10 (2006.01); H01L 29/45 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 21/0332 (2013.01); H01L 21/265 (2013.01); H01L 21/266 (2013.01); H01L 21/761 (2013.01); H01L 27/0629 (2013.01); H01L 29/1058 (2013.01); H01L 29/66893 (2013.01); H01L 29/66901 (2013.01); H01L 29/808 (2013.01); H01L 29/456 (2013.01); H01L 29/66128 (2013.01); H01L 29/8611 (2013.01);
Abstract

The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.


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