The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Sep. 02, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Yusuke Hamada, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/065 (2006.01); H03K 5/24 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H03K 5/24 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A semiconductor device includes: a first semiconductor chip including a first terminal at a first face side, a first load whose one end is connected to the first terminal, another end of the first load being to be connected to a power source potential, a second terminal at a second face side, a second load whose one end is connected to the second terminal, another end of the second load being to be connected to a ground potential, a first detection circuit that detects generation of potential difference at the first load, and a second detection circuit that detects generation of potential difference at the second load; and a second semiconductor chip including a connection terminal disposed at a face facing the first semiconductor chip; wherein the power source potential or the ground potential is to be connected through the connection terminal to the first or second terminal.


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