The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Mar. 02, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Toshifumi Minami, Yokohama, JP;

Hiroyuki Maeda, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 27/11517 (2017.01); H01L 27/11563 (2017.01); G01R 31/26 (2014.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); G01R 31/2644 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/585 (2013.01); H01L 27/11517 (2013.01); H01L 27/11563 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate including an element region, a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first-interconnect and a first well region, a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect, and a first circuit coupled to the second interconnect. The first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.


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