The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Sep. 06, 2015
Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventor:

Kwan-Woo Do, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 45/00 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 23/528 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
H01L 23/53266 (2013.01); G06F 12/0875 (2013.01); H01L 23/528 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G06F 2212/452 (2013.01); H01L 2924/0002 (2013.01);
Abstract

This patent document provides an electronic device including a semiconductor memory that can simplify a fabrication process and improve characteristics of a variable resistance element, and a method for fabricating the same. In one aspect, an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a substrate; a variable resistance element formed over the substrate and exhibiting different resistance states to store data; an interlayer insulating layer formed over the substrate to surround at least a portion of the variable resistance element; an upper electrode contact formed over the variable resistance element to penetrate a portion of the interlayer insulating layer and be in contact with the variable resistance element; and a metal wiring formed over the interlayer insulating layer, and configured to include a stacked structure of a tungsten layer and a barrier layer, wherein the barrier layer is in contact with the upper electrode contact and includes tungsten, boron and iridium.


Find Patent Forward Citations

Loading…