The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Feb. 20, 2015
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Poh Boon Leong, Cupertino, CA (US);

Hou Xian Loo, Singapore, SG;

Sehat Sutardja, Los Altos Hills, CA (US);

Wei Ding, Singapore, SG;

Huy Thong Nguyen, Singapore, SG;

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); H01L 23/522 (2006.01); H01F 27/28 (2006.01); H01L 23/498 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01L 23/64 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2006.01); H03H 7/42 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01F 27/28 (2013.01); H01L 23/49827 (2013.01); H01L 23/5221 (2013.01); H01L 23/5226 (2013.01); H01L 23/645 (2013.01); H01L 23/66 (2013.01); H01L 24/17 (2013.01); H01L 24/94 (2013.01); H01L 25/16 (2013.01); H05K 1/0213 (2013.01); H05K 1/181 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2223/6672 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/17051 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73257 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/94 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/19107 (2013.01); H03H 7/42 (2013.01); H05K 2201/1003 (2013.01);
Abstract

A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.


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