The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Mar. 07, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Takuya Hagiwara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); G03F 7/20 (2006.01); G03F 7/09 (2006.01); G03F 7/16 (2006.01); G03F 7/039 (2006.01); G03F 7/38 (2006.01); G03F 7/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0274 (2013.01); G03F 7/0392 (2013.01); G03F 7/094 (2013.01); G03F 7/162 (2013.01); G03F 7/168 (2013.01); G03F 7/2022 (2013.01); G03F 7/2041 (2013.01); G03F 7/327 (2013.01); G03F 7/38 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28017 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31055 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 29/66568 (2013.01);
Abstract

The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.


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