The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Nov. 02, 2016
Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventors:

Jae-Yun Yi, Icheon-si, KR;

Hong-Ju Suh, Icheon-si, KR;

Se-Dong Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/16 (2006.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G06F 3/061 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 12/0802 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G06F 2212/2024 (2013.01); G06F 2212/60 (2013.01);
Abstract

An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.


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