The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

May. 19, 2016
Applicant:

Gsi Technology, Inc., Sunnyvale, CA (US);

Inventors:

Lee-Lean Shu, Los Altos, CA (US);

Yoshinori Sato, San Jose, CA (US);

Assignee:

GSI TECHNOLOGY, INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/419 (2006.01); G11C 7/06 (2006.01); G11C 11/4096 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1039 (2013.01); G11C 7/06 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1087 (2013.01); G11C 11/419 (2013.01); G11C 7/1051 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2272 (2013.01);
Abstract

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.


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