The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Nov. 03, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Jin-Cheol Seo, Gyeonggi-do, KR;
Sung-Soo Chi, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 7/20 (2006.01); H03K 5/15 (2006.01); G11C 29/00 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G11C 7/20 (2013.01); G11C 29/789 (2013.01); H03K 5/15 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract
An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals.
Seo, Jin-Cheol. (2017). Electronic device and system that initializes logic circuits at different times by sequentially delaying a power up signal to a plurality of internal circuit blocks (U.S. Patent No. 9847107). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9847107
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile