The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Jul. 29, 2016
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Sreenivas Krishnan, Campbell, CA (US);

Nirmal Raj Saxena, Los Altos, CA (US);

Assignee:

INPHI CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); H04L 12/64 (2006.01); H04L 12/66 (2006.01); G06F 13/42 (2006.01); H04B 10/27 (2013.01); H04J 14/02 (2006.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); H04B 10/27 (2013.01); H04L 12/64 (2013.01); H04L 12/66 (2013.01); H04J 14/0267 (2013.01); H04L 49/15 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

A computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and can include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. The plurality of rack modules can each include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.


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