The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
Nov. 12, 2014
Xilinx, Inc., San Jose, CA (US);
Henry E. Styles, Menlo Park, CA (US);
Jeffrey M. Fifield, Boulder, CO (US);
Ralph D. Wittig, Menlo Park, CA (US);
Philip B. James-Roxby, Longmont, CO (US);
Sonal Santan, San Jose, CA (US);
Devadas Varma, Los Altos, CA (US);
Fernando J. Martinez Vallina, Sunnyvale, CA (US);
Sheng Zhou, San Jose, CA (US);
Charles Kwok-Wah Lo, Toronto, CA;
XILINX, INC., San Jose, CA (US);
Abstract
An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.