The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Jan. 14, 2013
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventor:

Frederick Perner, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 13/00 (2006.01); G11C 27/02 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G11C 7/1006 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 27/026 (2013.01); H03K 19/1776 (2013.01); G06F 2212/7201 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0057 (2013.01); G11C 2213/77 (2013.01);
Abstract

A method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage. The crosspoint array is configured in a second configuration and an input voltage is applied to the crosspoint array in the second configuration to produce a sense voltage. The setup voltage and the sense voltage compared to perform a logical operation on data stored in the crosspoint array. A system for performing nonvolatile memory array logic is also provided.


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