The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2017
Filed:
May. 20, 2011
Zongyou Shao, Tianjin, CN;
Xinchun Liu, Tianjin, CN;
Xiaojun Yang, Tianjin, CN;
Chenming Zheng, Tianjin, CN;
Ying Wang, Tianjin, CN;
Hui Wang, Tianjin, CN;
Shengjie Liu, Tianjin, CN;
Zhibin Hao, Tianjin, CN;
Faqing Liang, Tianjin, CN;
Wenhao Yao, Tianjin, CN;
Zongyou Shao, Tianjin, CN;
Xinchun Liu, Tianjin, CN;
Xiaojun Yang, Tianjin, CN;
Chenming Zheng, Tianjin, CN;
Ying Wang, Tianjin, CN;
Hui Wang, Tianjin, CN;
Shengjie Liu, Tianjin, CN;
Zhibin Hao, Tianjin, CN;
Faqing Liang, Tianjin, CN;
Wenhao Yao, Tianjin, CN;
DAWNING INFORMATION INDUSTRY CO., LTD., Tianjin, CN;
Abstract
The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.