The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2017
Filed:
Mar. 16, 2017
Analog Devices Global, Hamilton, BM;
Zhao Li, North York, CA;
Trevor Clifford Caldwell, Toronto, CA;
David Nelson Alldred, Toronto, CA;
Yunzhi Dong, Weehawken, NJ (US);
Prawal Man Shrestha, Somerville, MA (US);
Jialin Zhao, Santa Clara, CA (US);
Hajime Shibata, Toronto, CA;
Victor Kozlov, Toronto, CA;
Richard E. Schreier, New Castle, CA;
Wenhua W. Yang, Lexington, MA (US);
ANALOG DEVICES GLOBAL, Hamilton, BM;
Abstract
Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.