The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2017
Filed:
Jun. 03, 2016
Applicant:
Altera Corporation, San Jose, CA (US);
Inventor:
Ping Xiao, East Palo Alto, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/017 (2006.01); H03K 19/177 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1774 (2013.01); H01L 23/49827 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H03K 19/17708 (2013.01); H01L 2224/16155 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.