The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Aug. 02, 2016
Applicant:

National Chiao Tung University, Hsinchu, TW;

Inventor:

Chun-Yen Chang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 51/05 (2006.01); H01L 51/10 (2006.01); H01L 27/28 (2006.01); H01L 51/00 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0554 (2013.01); H01L 27/0886 (2013.01); H01L 27/283 (2013.01); H01L 51/0021 (2013.01); H01L 51/0516 (2013.01); H01L 51/0562 (2013.01); H01L 51/102 (2013.01); H01L 51/0529 (2013.01); H01L 51/107 (2013.01);
Abstract

A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.


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