The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Apr. 10, 2017
Applicant:

Advanced Optoelectronic Technology, Inc., Hsinchu Hsien, TW;

Inventors:

Chao-Hsiung Chang, Hsinchu, TW;

Hou-Te Lin, Hsinchu, TW;

Pin-Chuan Chen, Hsinchu, TW;

Lung-Hsin Chen, Hsinchu, TW;

Wen-Liang Tseng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/38 (2010.01); H01L 33/44 (2010.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/382 (2013.01); H01L 33/387 (2013.01); H01L 33/44 (2013.01); H01L 33/486 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method for manufacturing a light emitting diode (LED) die includes providing an LED die including a substrate, an N type semiconductor layer, an active layer, and a P type semiconductor layer grown on the substrate in sequence. The N type semiconductor layer, the active layer, and the P type semiconductor layer are etched to define a plurality of recesses and a groove. An insulating layer to cover side surfaces of the recesses and the P type semiconductor layer is formed and a portion of the insulating layer is etched to define an opening to expose a top portion of the P type semiconductor layer. A pair of electrodes is formed and the LED die is cut along the groove to obtain an individual LED die.


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