The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Dec. 28, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Yong-Woo Yoo, Paju-si, KR;

Sang-Hyun Bae, Daegu-si, KR;

Ju-Yeon Kim, Goyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 21/44 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 27/32 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78618 (2013.01); H01L 21/44 (2013.01); H01L 27/1225 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G02F 1/1368 (2013.01); H01L 27/3262 (2013.01);
Abstract

A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.


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