The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Jul. 28, 2017
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Chi-Yu Yeh, Hsin-Chu, TW;

Chen-Ming Hu, Hsin-Chu, TW;

Yen-Shih Huang, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); G09G 3/3225 (2016.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); G09G 3/3225 (2013.01); H01L 27/3265 (2013.01); H01L 27/3276 (2013.01); H01L 29/78696 (2013.01); G09G 2300/0819 (2013.01); G09G 2320/0233 (2013.01);
Abstract

A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.


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