The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Sep. 10, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ji Hun Kim, Hwaseong-si, KR;

Ilgweon Kim, Hwaseong-si, KR;

Junhwa Song, Incheon, KR;

Jeonghoon Oh, Seoul, KR;

WonSeok Yoo, Hwaseong-si, KR;

Eun-Sun Lee, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 27/108 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/76224 (2013.01); H01L 21/823412 (2013.01); H01L 21/823807 (2013.01); H01L 27/1085 (2013.01); H01L 27/10805 (2013.01); H01L 27/10814 (2013.01); H01L 27/10817 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 27/10891 (2013.01); H01L 28/91 (2013.01);
Abstract

A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.


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