The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Dec. 04, 2015
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

Minghao Shen, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/24 (2013.01); H01L 24/49 (2013.01); H01L 24/82 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 2224/2405 (2013.01); H01L 2224/24137 (2013.01);
Abstract

An integrated circuit package that includes an integrated circuit die, a redistribution substrate, a wirebond interconnect and a package substrate is disclosed. The redistribution substrate is formed on the integrated circuit die and may be wider than the integrated circuit die. The package substrate is formed below the integrated circuit die. The wirebond interconnect may have one of its ends attached to the redistribution substrate and another end attached to the package substrate. In addition to that, another integrated circuit die may be formed between the redistribution substrate and the package substrate. The integrated circuit dies may communicate with each other through the redistribution substrate. In addition to that, a method to manufacture the integrated circuit package may also be disclosed.


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