The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Dec. 28, 2015
Applicants:

Junggun You, Ansan-si, KR;

Sukhoon Jeong, Suwon-si, KR;

Inventors:

Junggun You, Ansan-si, KR;

Sukhoon Jeong, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 21/823828 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.


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