The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Jan. 28, 2015
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Masato Endo, Yokohama, JP;

Kazunori Masuda, Yokohama, JP;

Yukio Nishida, Yokohama, JP;

Naoya Kami, Fujisawa, JP;

Yuuichi Tatsumi, Setagaya, JP;

Naoyuki Kondo, Kamakura, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/11529 (2017.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 23/53295 (2013.01); H01L 27/11529 (2013.01); H01L 23/5222 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 27/11519 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.


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