The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Nov. 03, 2016
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Soon-cheon Seo, Glenmont, NY (US);

Linus Jang, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01); H01L 21/027 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); H01L 21/0274 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/4238 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823412 (2013.01); H01L 21/84 (2013.01);
Abstract

After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.


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