Shift register and display device using the same

Abstract

Discussed is a shift register capable of reducing a circuit area through simplification of a logic circuit configuration. The shift register according to an embodiment includes stages each selectively executing a forward scan and a backward scan. Each stage includes a pull-up transistor for generating a first clock under control of a control node, as an output thereof, a pull-down transistor for generating a gate-off voltage under control of a third clock, as an output thereof, a first transistor for setting and resetting the control node during the forward scan while resetting the control node during the backward scan, under control of a fourth clock, using output signals from a previous stage, and a second transistor for setting and resetting the control node during the backward scan while resetting the control node during the forward scan, under control of a second clock, using output signals from a next stage.