The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2017
Filed:
May. 24, 2016
Altera Corporation, San Jose, CA (US);
Kyung Suk Oh, Cupertino, CA (US);
Yee Huan Yew, Bayan Lepas, MY;
Chee Cheong Tan, Georgetown, MY;
Mei See Chin, Gelugor, MY;
Wai Ling Lee, Bayan Lepas, MY;
Loke Yip Foo, Ipoh, MY;
Chooi Ian Loh, Sungai Bakap, MY;
Hui Lee Teng, Gelugor, MY;
Altera Corporation, San Jose, CA (US);
Abstract
The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.