The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

May. 20, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Scott D. McLeod, Campbell, CA (US);

Hsung Jai Im, San Jose, CA (US);

Stanley Y. Chen, Cupertino, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/04 (2006.01); H03K 3/012 (2006.01); H03K 3/3568 (2006.01); G01R 31/28 (2006.01); G01R 31/3185 (2006.01); H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
G01R 31/041 (2013.01); G01R 31/2884 (2013.01); G01R 31/318572 (2013.01); H03K 3/012 (2013.01); H03K 19/017527 (2013.01); H03K 19/018514 (2013.01); H04L 25/0272 (2013.01); H03K 3/3568 (2013.01);
Abstract

In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.


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