The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Feb. 29, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Takeshi Miyamae, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/37 (2006.01); H03M 13/09 (2006.01); H03M 13/00 (2006.01); G06F 12/08 (2016.01); G06F 11/20 (2006.01); G06F 11/14 (2006.01); G06F 11/10 (2006.01); G06F 12/0868 (2016.01); G06F 12/0804 (2016.01);
U.S. Cl.
CPC ...
H03M 13/3761 (2013.01); G06F 11/108 (2013.01); G06F 11/1076 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 11/1471 (2013.01); G06F 11/2094 (2013.01); G06F 2211/1059 (2013.01); H03M 13/093 (2013.01); H03M 13/611 (2013.01);
Abstract

A storage system includes a first information processor, a second information processor, and a superordinate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating, a second memory device stores therein the generated difference data, and a data transmitter that transmits the stored difference data to the second information processor. The second information processor includes a third memory device that stores therein the parity, a data receiver that receives the difference data transmitted from the data transmitter, and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the received difference data to the stored parity before the updating.


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