The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2017
Filed:
Apr. 06, 2017
Applicant:
Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;
Inventors:
Scott E. Thompson, Gainesville, FL (US);
Lawrence T. Clark, Phoenix, AZ (US);
Assignee:
Mie Fujitsu Semiconductor Limited, Kuwana, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/00 (2006.01); H01L 29/10 (2006.01); H01L 27/118 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); G11C 11/412 (2013.01); H01L 27/11807 (2013.01); H01L 29/1095 (2013.01);
Abstract
Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.