The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9837995 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 05, 2017

Filed:

Jul. 27, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Fadi Adel Hamdan, Austin, TX (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); H03K 3/037 (2006.01); G06F 13/362 (2006.01); H03K 5/131 (2014.01); H03K 5/135 (2006.01); G06F 1/10 (2006.01); G06F 1/32 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 1/3237 (2013.01); G06F 13/362 (2013.01); H03K 3/0375 (2013.01); H03K 5/131 (2013.01); H03K 5/135 (2013.01); H03K 2005/00013 (2013.01); H03K 2005/00058 (2013.01); Y02B 60/1221 (2013.01);
Abstract

An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal. The apparatus further includes an output circuit of the CGC. The output circuit is coupled to the delay circuit and to the latch. The output circuit is configured to generate a master clock signal based on the clock signal and the second signal. An edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal.


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