The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Sep. 25, 2015
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiangbo Chen, Beijing, CN;

Jun Cheng, Beijing, CN;

Chunsheng Jiang, Beijing, CN;

Xiaodi Liu, Beijing, CN;

Xiangyong Kong, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 21/77 (2017.01); H01L 51/56 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); H01L 21/77 (2013.01); H01L 51/56 (2013.01); H01L 2227/323 (2013.01);
Abstract

Embodiments of the invention provide an array substrate and a method of manufacturing the same. The method comprises: forming a gate electrode pattern, a gate insulation layer, an active layer pattern and an etching stopping layer on a substrate; forming a photoresist layer on the etching stopping layer; performing a single patterning process on the photoresist layer, such that photoresist in the first region is partially etched off, photoresist in the second region is completely etched off, and photoresist in the third region is completely remained; and performing a single etching process, such that residual photoresist in the first region and a portion of the etching stopping layer in the first region are etched off, and at the same time, a portion of the etching stopping layer and a portion of the gate insulation layer in the second region are etched off.


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