The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2017
Filed:
Aug. 31, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Dong Yean Oh, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/268 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2454 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/7827 (2013.01); H01L 29/7831 (2013.01); H01L 45/065 (2013.01); H01L 45/126 (2013.01); H01L 45/1233 (2013.01); H01L 45/1683 (2013.01); H01L 45/06 (2013.01);
Abstract
In a method of manufacturing a semiconductor integrated circuit device, a pillar may be formed on a semiconductor substrate. A hard mask pattern may be formed on a top surface and a portion of a sidewall of the pillar. An electric field-buffering region may be formed in the sidewall of the pillar. A gate insulating layer may be formed on an outer surface of the pillar. A gate may be formed on the gate insulating layer.