The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Nov. 23, 2016
Applicants:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Omid Rowhani, Kettleby, CA;

Jason P. Cain, Austin, TX (US);

Ioan Cordos, Thornhill, CA;

Michael Davinson Sherriff, Mississauga, CA;

Hoang Q. Dao, Austin, TX (US);

Assignees:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

ATI Technologies ULC, Markham, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 23/528 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); H01L 23/528 (2013.01); H01L 29/0696 (2013.01);
Abstract

Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.


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