The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Dec. 01, 2015
Applicant:

Hgst, Inc., San Jose, CA (US);

Inventor:

Mac D. Apodaca, San Jose, CA (US);

Assignee:

HGST, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/06 (2006.01); H01L 21/02 (2006.01); H01L 29/26 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02568 (2013.01); H01L 21/02381 (2013.01); H01L 21/02485 (2013.01); H01L 21/02494 (2013.01); H01L 29/26 (2013.01);
Abstract

A method for producing a substantially planar surface for semiconductor processing to improve lithography, planarization, and other process steps that benefit from a flat substrate. The method includes depositing a first alloy to form a first layer on a substrate. The first layer has a center high deposition, meaning the height in the center of the substrate is higher than the height at the edges of the substrate. The method further includes depositing a second alloy on the first layer to form a second layer. The first alloy has a different composition than the second alloy. In such a method the net deposition is substantially planar reducing or eliminating deposition induced long-range distortions that might occur across a substrate.


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