The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Nov. 10, 2015
Applicants:

Mediatek Inc., Hsin-Chu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Po-Han Wang, Taipei, TW;

Cheng-Hsuan Li, Kaohsiung, TW;

Chia-Lin Yang, Taipei, TW;

Assignees:

MEDIATEK INC., Hsin-Chu, TW;

NATIONAL TAIWAN UNIVERSITY, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 3/06 (2006.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 12/0895 (2016.01); G06F 12/0864 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0895 (2013.01); G06F 12/0864 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/601 (2013.01);
Abstract

A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.


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