The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Jun. 19, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Yaoxie Zheng, Beijing, CN;

Zheng Bian, Beijing, CN;

Jinwei Zhu, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G02F 1/13 (2006.01); H01L 27/12 (2006.01); H01L 21/66 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1309 (2013.01); G02F 1/13458 (2013.01); H01L 22/32 (2013.01); H01L 27/124 (2013.01); H01L 27/1259 (2013.01); G02F 1/13452 (2013.01);
Abstract

There are provided an array substrate and method for manufacturing the same, a display panel and method for testing the same, and a display apparatus. The array substrate comprises a display region and at least one bond region located outside of the display region; wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; the array substrate further comprises one or more test regions corresponding to arbitrary one or more of the at least one bond region; wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires. The present invention implements a lead wire open test for a display panel for which the lead wire open test cannot be implemented in a traditional test mode.


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