The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2017
Filed:
Sep. 18, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Min-Seok Shin, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/56 (2006.01); H03M 1/36 (2006.01); H03K 21/10 (2006.01); H03K 19/21 (2006.01); G11C 27/02 (2006.01); H03K 4/02 (2006.01); H04N 5/378 (2011.01); H04N 5/376 (2011.01);
U.S. Cl.
CPC ...
H03M 1/56 (2013.01); G11C 27/02 (2013.01); H03K 4/02 (2013.01); H03K 19/21 (2013.01); H03K 21/10 (2013.01); H03M 1/1245 (2013.01); H03M 1/36 (2013.01); H04N 5/376 (2013.01); H04N 5/378 (2013.01); H03M 1/123 (2013.01);
Abstract
A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.