The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Oct. 19, 2016
Applicant:

The Florida State University Research Foundation, Inc., Tallahassee, FL (US);

Inventors:

Hui Li, Tallahassee, FL (US);

Yanjun Shi, Tallahassee, FL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/084 (2006.01); H02M 7/537 (2006.01); H02M 1/44 (2007.01);
U.S. Cl.
CPC ...
H02M 7/537 (2013.01); H02M 1/44 (2013.01);
Abstract

A self-balanced modulation method and a closed-loop magnetic flux rebalancing control method for parallel multilevel inverters. The combination of the two methods provides for balancing of the magnetic flux of the inter-cell transformers (ICTs) of the parallel multilevel inverters without deteriorating the quality of the output voltage. In various embodiments a parallel multi-level inverter modulator is provide including a multi-channel comparator to generate a multiplexed digitized ideal waveform for a parallel multi-level inverter and a finite state machine (FSM) module coupled to the parallel multi-channel comparator, the FSM module to receive the multiplexed digitized ideal waveform and to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter. The system and method provides for optimization of the output voltage spectrum without influence the magnetic balancing.


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