The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Sep. 30, 2011
Applicants:

Jayesh Nath, Santa Clara, CA (US);

Ying Shen, Chapel Hill, NC (US);

Inventors:

Jayesh Nath, Santa Clara, CA (US);

Ying Shen, Chapel Hill, NC (US);

Assignee:

Aviat U.S., Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01P 3/08 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01P 3/081 (2013.01); H01L 23/481 (2013.01); H01L 23/66 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6683 (2013.01); H01L 2924/0002 (2013.01); Y10T 29/49155 (2015.01);
Abstract

Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.


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