The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Dec. 01, 2015
Applicant:

Samsung Display Co., Ltd, Yongin, Gyeonggi-Do, KR;

Inventor:

Je-Hun Lee, Yongin, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); H01L 51/05 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 51/10 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0512 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66742 (2013.01); H01L 29/786 (2013.01); H01L 51/107 (2013.01);
Abstract

Provided is a thin film transistor array substrate, including a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor pattern formed on the gate insulating layer and including a channel region overlapping the gate electrode, a source electrode and a drain electrode formed on the semiconductor pattern and facing each other with a first opening exposing the channel region therebetween, a first protective layer formed on the gate insulating layer to cover the source electrode, the drain electrode and the semiconductor pattern and a metal oxide layer formed along a surface of the first protective layer.


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